combinational circuit
英
美
网络 组合电路; 组合逻辑电路
双语例句
- A combinational circuit that has three inputs that are an augend, D, an addend, E, and carry digit transferred from another digit place, F, and two outputs that are a '.
三个输入端是：被加数d、加数e以及从另一个数位传来的进位数f；两个输出端是：无进位和数t及新的进位数r。 - Test generation and optimization of bridging faults diagnosis in combinational circuit
组合电路桥接故障诊断的测试生成及优化 - Evolutionary design of combinational circuit based on game genetic algorithm
基于博弈遗传算法的组合电路进化设计 - Multiplexer is a kind of combinational logic circuit, which can be selected an in-put datum among several data and sent it to out-put port.
数据选择器是一种能从多个输入数据中有选择地将一个输入数据送到输出端的组合逻辑电路。 - If the combinational logic circuit is only one output, called the single-output combinational logic circuit;
如果组合逻辑电路只有一个输出，称为单输出组合逻辑电路； - The method of judge and remove in the phenomenon of race and hazard of the combinational logic circuit
组合逻辑电路中的竞争冒险现象的判断和消除 - Design of ternary combinational circuit by the simplification rules of binary algebra
利用二值代数的化简法则进行三值组合电路的设计 - A Functional Level Test Generation Method of Combinational Circuit with Critical Binary Tree
组合电路功能级测试生成的临界二元树方法 - This paper analyzes the relations of Boolean partial derivative and Boolean difference, gives the equation of the test set for the double fault of a combinational circuit, and introduces the concept of the odd set.
分析了布尔偏导数与布尔差分的关系，给出了基于布尔偏导数的组合电路双故障测试集的方程，引入了奇集合的概念。 - The Tests for Bridging Faults and Short-Diode Faults in Combinational Circuit
组合线路中的桥接故障及二极管短路故障 - The Application of Data Selector in the Combinational Logic Circuit
数据选择器在组合逻辑电路中的应用 - The Study of D-Algorithm for Trouble Test Generation in Combinational Circuit
组合电路的故障测试生成D算法研究 - This algorithm can increase only sensitization condition in fan-out point and decrease signal conflict to decrease trace so as to accelerate test generation for large scaled combinational circuit and printed Circuit Board.
该算法用于大型组合电路的测试生成，可以增加扇出分支处的唯一敏化条件，减少信号冲突和回溯次数，大大加快了大规模组合电路以及印制电路板的测试生成速度。 - This paper presented and expounded the principle and way of design in combinational logic circuit based on exclusive-OR gate, pointed out the applicability of this way and the superiority in the optimization of logic design and improvement of circuit function in combination with concrete living examples.
提出井阐述了以异或门为基础的组合逻辑电路的设计原理和设计方法，结合具体实例，指明了谊方法的适用范围，以及在优化逻辑设计、提高电路性能方面的优越性。 - We propose a gate level algorithm for average power estimation in combinational circuit under the unit delay model and the general delay model.
提出一种基于ROBDD图和时延差的组合电路门级平均功耗估算算法，该算法适用于单位延迟模型和一般的延迟模型。 - Boolean Process Based Waveform Simulation for Combinational Circuit
基于布尔过程的组合电路波形模拟 - Based on a Hopfield neural network model for combinational circuit test generation, a test generation algorithm with global searching ability of chaotic neural networks and a self-adaptive test generation based on genetic algorithm is analyzed.
基于组合电路测试生成的Hopfield神经网络模型，讨论分析了利用混沌神经网络的全局搜索能力进行测试生成的有效算法和基于遗传算法的自适应测试生成。 - Application of the Coding to the Design of Combinational Circuit
编码在组合电路设计中的运用 - This paper briefly introduces the basic method of transforming data selector into combinational logic circuit of other functions.
简述了用数据选择器转换为其它功能组合逻辑电路的基本方法。 - Furthermore, the sequential circuit design shows that it may lead to a simpler excitation function and combinational circuit because of its more powerful logic function.
此外，由时序电路的设计实例，也证实了因它的功能较强而能导致较简单的激励函数与组合电路。 - Combinational Circuit Design Algorithm and Software Framework
组合电路设计演化算法及软件框架 - CMOS Combinational Circuit Leakage Power Reduction Using Genetic Algorithms
利用遗传算法实现CMOS组合电路静态功耗优化 - Digital multiplexer and matrix equation in designing combinational logic circuit
采用数据选择器和矩阵方程法设计组合逻辑电路 - Test for internal fault and multiple fault of combinational circuit
组合电路内部故障及多故障测试 - The method of optimization is classified into two categories: ( 1) combinational optimization method, which is the optimizational method of combinational circuit is directly used for the sequence circuit.
优化的方法大致可分为两类：（1）组合优化方法，即将组合电路的优化方法直接用于时序电路。 - Fault diagnosis of the control circuit is researched, and some relative diagnosis ways are given for the test of a few fault phenomena of the combinational logic circuit and the sequential circuit.
通过对控制电路系统故障诊断的研究，对组合逻辑电路的多种故障现象以及时序逻辑电路给出了对应的测试与诊断方法，并提出了控制系统对转子中心位置的搜索方法。 - The test pattern generation algorithms for combinational logic circuit and the fault types were discussed.
讨论了组合逻辑电路的故障诊断的方法，故障的类型。 - The digital part includes closed loop oscillator, frequency divider, combinational logic circuit, non-overlapping clock generation circuit.
数字部分包含环形振荡器、分频器、组合逻辑门、非交叠时钟产生电路。 - The main contents are as follows: Combinational circuit verification is an important aspect and foundation of formal verification of digital integrated circuits.
主要内容包括：组合电路验证是数字集成电路形式化设计验证的重用方面。 - The system has simulated three different type experiments, namely, physics pendulum experiment and combinational circuit experiment, electric and electronic disciplines decoder experiment.
系统模拟3个不同类型的实验，分别是物理学科的单摆实验和组合电路实验，电工电子学科的译码器实验。